The invention is directed to an integrated circuit in complementary circuit technology having a substrate bias generator.
In circuits of this type, the semiconductor substrate does not lie at the ground potential V.sub.SS of the circuit but at a substrate bias V.sub.BB which is generated by the substrate bias generator. Given a semiconductor substrate of p-conductive material having an inserted, n-conductive well-shaped semiconductor zone, a negative substrate bias of about -2 through -3 volts is used. The source regions of field effect transistors, which are provided outside of the well-shaped semiconductor zone on the semiconductor substrate, are connected to the ground potential V.sub.SS.
At the moment the positive supply voltage V.sub.DD is switched on, the p-conductive semiconductor substrate is initially "floating", i.e., it is disconnected from external potentials. The depletion layer capacitances which are present, first, between the well-shaped semiconductor zone and the substrate and, second, between the source regions connected to the grounded potential and the substrate, can thereby be temporarily charged to a positive bias, which persists until the substrate bias generator takes effect and is replaced as the negative substrate bias gradually builds up. Positive biases, however, represent a high safety risk for the integrated circuit since a latch-up effect can be triggered which generally means the destruction of the integrated circuit.
For an understanding of the latch-up effect, one can assume that four successive semiconductor layers alternating in conductivity type are generally present between a terminal of a field effect transistor of the first channel type lying in the well-shaped semiconductor zone and a terminal of a field effect transistor of the second channel type placed outside of this zone on the semiconductor substrate, whereby the one terminal region of the former transistor is formed by the first semiconductor layer, the well-shaped semiconductor zone is formed by the second layer, the semiconductor substrate is formed by the third layer, and the one terminal region of the latter transistor is formed by the fourth semiconductor layer. Given a positive bias of the semiconductor substrate, the p-n junction between the third and the fourth semiconductor layers can be forward biased to such a degree that a current path arises between the transistor terminals, attributable to a parasitic thyristor effect within this four-layer structure. The current path also remains after a dismantling of the positive substrate bias and can thermally overload the integrated circuit.